A reception circuit capable of receiving signals of various transmission speeds (bit-rates) at respective optimal performance is proposed (for example, see Patent Document 1). Such a reception circuit uses a bit-rate discrimination circuit for automatically discriminating the bit-rate of an input signal.
FIG. 21 shows the bit-rate discrimination circuit described in the Patent Document 1. In FIG. 21, a reference numeral 1 denotes an input terminal; 2 denotes an output terminal; 3 denotes a delay circuit; 4 denotes an exclusive OR circuit; 5 denote a mean value detector; 6 denotes a level decision circuit; and 7 denotes a reference voltage input terminal. FIG. 22 shows waveforms at various points A-D in the bit-rate discrimination circuit shown in FIG. 21. In FIG. 22, the waveform A is that of an input signal; the waveform B is that of an output signal from the exclusive OR circuit 4; the waveform C is that of an output signal from the mean value detector 5; and the waveform D is that of an output signal from the level decision circuit 6.
The conventional bit-rate discrimination circuit shown in FIG. 21 has the delay circuit 3 and the exclusive OR circuit 4 at the input stage. When an input signal having the waveform A (input signal A) is fed to the input terminal 1, pulses are output at each rise and fall edges of the input signal A as shown as the waveform B, and the pulse width of the pulses are determined by the delay time of the delay circuit 3. The density of the pulses is high if the bit-rate of the input signal is high, and is low if the bit-rate of the input signal is low. The mean value detector 5 outputs high voltage for a high bit-rate input signal and low voltage for a low bit-rate input signal by averaging the density of the pulses in the input signal. The level decision circuit 6 compares the voltage level output from the mean value detector 5 with a reference voltage (Vref), and outputs a control signal having the waveform D (control signal D).
Patent Document 1: Japanese Laid-Open Patent Application No. 2000-40960
However, the conventional bit-rate discrimination circuit shown in FIG. 21 can not discriminate the bit-rate accurately in the case of feeding back the control signal as the result of discrimination. FIG. 23 is a block diagram showing a multi bit-rate reception circuit using the conventional bit-rate discrimination circuit, which illustrates a case in which the above problem occurs. In FIG. 23, a reference numeral 1 denotes an input terminal; 8 denotes a variable gain/bandwidth preamplifier; 9 denotes a gain/bandwidth control terminal; 10 denotes a limiting amplifier; 11 denotes the bit-rate discrimination circuit shown in FIG. 21; 12 and 13 denote differential output terminals. This multi bit-rate reception circuit discriminates the bit-rate of the input signal using the bit-rate discrimination circuit 11, and controls the bandwidth and gain of the variable gain/bandwidth preamplifier 8 such that the bandwidth and gain are optimized in dependence on the bit-rate of the input signal.
When a low bit-rate input signal is fed, the bit-rate discrimination circuit 11 outputs a low bit-rate determination, which controls the variable gain/bandwidth preamplifier 8 to lower its upper limit frequency of band and to increase its gain, resulting in the increase in receiver sensitivity. However, if the bit-rate of the input signal is switched from low bit-rate to high bit-rate, the high frequency component of a signal fed to the bit-rate discrimination circuit 11 is lost because the upper limit frequency of the variable gain/bandwidth preamplifier 8 is low. Consequently, the bit-rate discrimination circuit can not discriminate the bit-rate of the signal accurately.